Analysis of probability and energy of nanometre CMOS circuits in presence of noise

Introduction: As the feature sizes of semiconductor devices decrease, their behaviour becomes increasingly ‘probabilistic’ owing to sources such as thermal noise [1], ground bounce [2] and process variations [3]. Enhancing the robustness of circuits and systems to this probabilistic behaviour introduces some redundancy. Thus, there is a fundamental tradeoff between robustness and energy efficiency. This tradeoff has been exploited to enable energy efficient computing platforms via probabilistic computing [4]. The basic element of this approach is a probabilistic CMOS (PCMOS) device, which is a noisy CMOS device that computes correctly with probability p. In our previous work, characterisation of a PCMOS switch [5], a method to use these switches to build probabilistic architectures [6], and the tradeoffs between energy, performance and p of this switch [7] have been studied. In this Letter, we analyse the probabilistic behaviour of larger circuits by first developing probability models of primitive gates, which are then input to a graphbased model to find the probabilities of larger circuits.